How to Identify Suitable Gate Dielectrics for Transistors based on Two-Dimensional Semiconductors
Theresia Knobloch, Quentin Smets, Anton E. O. Persson, Pedram Khakbaz, Christoph Wilhelmer, Dennis Lin, Zherui Han, Yunyan Chung, Kevin P. OBrien, Chelsey Dorow, Cormac OCoileain, Mario Lanza, Dominic Waldhoer, Alexander Karl, Kailang Liu, Tianyou Zhai, Hailin Peng, Congwei Tan, Xiao Renshaw Wang, Georg S. Duesberg, John Robertson, Uygar Avci, Iuliana Radu, Eric Pop, Cesar J. Lockhart de la Rosa, Tibor Grasser
公開日: 2025/9/24
Abstract
The recent progress in nanosheet transistors has established two-dimensional (2D) semiconductors as viable candidates for future ultra-scaled electronic devices. Next to reducing contact resistance, identifying good gate dielectrics is a fundamental challenge, as the dielectric/channel interface dramatically impacts virtually all performance parameters. While several promising gate dielectrics have recently been reported, the evaluation of their quality and suitability is often fragmentary and focused on selected important performance metrics of the gate stack, such as the capacitive gate control, leakage currents, reliability, and ease of fabrication and integration. However, identifying a suitable gate stack is a complex problem that has not yet been approached systematically. In this perspective, we aim to formulate general criteria for good gate dielectrics.