📝 SummarXiv

Abstract

The continuing advancement of memory technology has not only fueled a surge in performance, but also substantially exacerbate reliability challenges. Traditional solutions have primarily focused on improving the efficiency of protection schemes, i.e., Error Correction Codes (ECC), under the assumption that allocating additional memory space for parity data is always expensive and therefore not a scalable solution. We break the stereotype by proposing an orthogonal approach that provides additional, cost-effective memory space for resilient memory design. In particular, we recognize that ECC chips (used for parity storage) do not necessarily require the same performance level as regular data chips. This offers two-fold benefits: First, the bandwidth originally provisioned for a regular-performance ECC chip can instead be used to accommodate multiple low-performance chips. Second, the cost of ECC chips can be effectively reduced, as lower performance often correlates with lower expense. In addition, we observe that server-class memory chips are often provisioned with ample, yet underutilized I/O resources. This further offers the opportunity to repurpose these resources to enable flexible on-DIMM interconnections. Based on the above two insights, we finally propose SCREME, a scalable memory framework leverages cost-effective, albeit slower, chips -- naturally produced during rapid technology evolution -- to meet the growing reliability demands driven by this evolution.