📝 SummarXiv

Abstract

Continued miniaturization of transistors is critical for sustaining advances in computing performance, energy efficiency, and integration density. A central nanoscale challenge is controlling gate leakage through ultrathin dielectrics. In evaluating candidate insulators, permittivity and bandgap are often emphasized; however, interfaces between two-dimensional (2D) semiconductors and gate dielectrics typically form a van der Waals (vdW) gap whose electronic properties are underappreciated. Using first-principles calculations and analytical modeling supported by experiment, we find typical vdW gaps of about 1.4 \AA{} with an effective dielectric constant near 2, which adds roughly 2.7 \AA{} to the equivalent oxide thickness (EOT). The vdW gap serves as an additional tunneling barrier that can reduce gate leakage by one to two orders of magnitude, but it also introduces parasitic capacitance that can offset the benefits of high-k dielectrics. We introduce a dimensionless figure of merit that combines dielectric screening, tunneling suppression, and thickness-dependent permittivity of ultrathin oxides to predict the minimum achievable EOT for a target gate-leakage current in the presence of a vdW gap. Although some materials may benefit from vdW gaps, our results indicate they often impose severe constraints on further scaling. In particular, due to the vdW gap, most currently considered insulators are unlikely to scale to an EOT of 5 \AA{} as targeted by the IRDS roadmap for future nodes. As a potential alternative, we examine ``zippered'' structures in which quasi-covalent bonding between 2D layers eliminates the vdW gap while avoiding dangling bonds.