📝 SummarXiv

Abstract

We review two magnetic tunnel junction (MTJ) approaches for compact, low-power, CMOS-integrated true random number generation (TRNG). The first employs passive-read, easy-plane superparamagnetic MTJs (sMTJs) that generate thermal-fluctuation-driven bit streams at $0.5$--$1$~Gb/s per device. The second uses MTJs with magnetically stable free layers, operated with stochastic write pulses to achieve switching probabilities of about $0.5$ (\emph{i.e.}, write error rates of $\simeq 0.5$), achieving $\gtrsim 0.1$~Gb/s per device; we refer to these as stochastic-write MTJs (SW-MTJs). Randomness from both approaches has been validated using the NIST~SP800 test suites. The sMTJ approach uses a read-only cell with low power and can be compatible with most advanced CMOS nodes, while SW-MTJs leverage standard CMOS MTJ process flows, enabling co-integration with embedded spin-transfer torque magnetic random access memory (STT-MRAM). Both approaches can achieve deep sub-0.01~$\mu$m$^2$ MTJ footprints and offer orders-of-magnitude better energy efficiency than CPU/GPU-based generators, enabling placement near logic for high-throughput random bit-streams for probabilistic computing, statistical modeling, and cryptography. In terms of performance, sMTJs generally suit applications requiring very high data-rate random bits near logic processors, such as probabilistic computing or large-scale statistical modeling. By contrast, SW-MTJs are an attractive option for edge-oriented microcontrollers, providing entropy sources for computing or cryptographic enhancement. We highlight the strengths, limitations, and integration challenges of each approach, emphasizing the need to reduce device-to-device variability in sMTJs -- particularly by mitigating magnetostriction-induced in-plane anisotropy -- and to improve temporal stability in SW-MTJs for robust, large-scale deployment.