📝 SummarXiv

Abstract

Simulating computationally hard fermionic systems is a promising application of quantum computing. However, mapping nonlocal fermionic operators to qubits often produces deep circuits, rendering such simulations impractical on near-term hardware. We introduce two Majorana swap network techniques for variational quantum eigensolvers that reduce circuit depth and two-qubit gate count, thereby limiting error accumulation. First, we develop a cyclic compilation algorithm that localizes all two-particle interaction terms in a general fermionic Hamiltonian that contains $\mathcal{O}(n^4)$ such terms, using only $\mathcal{O}(n^3)$ auxiliary Majorana-swap gates, where $n$ is the number of fermionic modes. This algorithm targets all-to-all qubit connectivity (e.g., trapped-ion processors) and can be used to compactify UCCGSD circuits. Second, we design a Majorana swap network for the UpCCGSD variational ansatz, which is already more compact than UCCGSD. Our network achieves asymptotic reductions in circuit depth and gate count of approximately 50% and 20%, respectively, under all-to-all connectivity. For the more restricted $2\times N$ connectivity, the reductions are even larger -- about 55% (circuit depth) and 40% (gate count). These improvements translate directly into increased robustness to hardware noise, as demonstrated by numerical simulations on representative examples.